project / 2025-26
Computer architecture / verification
AXIOM-4
A 4-bit RISC-inspired microprocessor with banked memory, a custom ISA, and a verification workflow built in public.
- built with Verilog 2005 / Icarus Verilog / GTKWave / Python
- source View source ↗
notes on the build
Challenge
AXIOM-4 is a low-level architecture project where the core decisions stay visible. The datapath, instruction set, memory model, and verification flow all have to be defined directly.
Approach
The processor is intentionally compact but not trivial:
- a 4-bit arithmetic and logic datapath
- a 256-byte unified address space using banked memory
- a custom ISA
- a dedicated assembler
- simulation and waveform inspection through Icarus Verilog and GTKWave
That combination keeps the architecture visible at every layer.
Why it matters
It is useful because it keeps the fundamentals exposed. There is no separation between the architecture itself and the tooling needed to test it.
Why it stays in the portfolio
It stays here because it reflects the kind of systems work that improves judgment higher up the stack as well.
what mattered
- 4-bit datapath with a 256-byte banked memory model.
- 2-stage finite-state execution model for predictable timing.
- Custom assembler and verification tooling included alongside architecture documentation.
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