project / 2025-26
Computer architecture / verification
AXIOM-4
A 4-bit RISC-inspired microprocessor with banked memory, a custom ISA, and a verification workflow built in public.
- built with Verilog 2005 / Icarus Verilog / GTKWave / Python
- source View source ↗
notes on the build
Challenge
AXIOM-4 is the kind of project that strips away abstraction. You do not get to hide behind frameworks when you are defining the datapath, instruction set, memory model, and verification flow yourself.
Approach
The processor is intentionally compact but not trivial:
- a 4-bit arithmetic and logic datapath
- a 256-byte unified address space using banked memory
- a custom ISA
- a dedicated assembler
- simulation and waveform inspection through Icarus Verilog and GTKWave
That combination makes it educational in the best sense. The architecture stays visible at every layer.
Projects like this are useful because they make every systems decision concrete.
Why it matters
AXIOM-4 says something useful about engineering temperament. It shows patience with fundamentals, interest in verification, and a willingness to build tooling around the core idea instead of stopping at the headline.
Why it stays in the portfolio
It stays here because it reminds me that judgment is easier to trust when it rests on fundamentals. Building at this level makes everything higher up the stack feel sharper.
what mattered
- 4-bit datapath with a 256-byte banked memory model.
- 2-stage finite-state execution model for predictable timing.
- Custom assembler and verification tooling included alongside architecture documentation.
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